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| Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) FEATURES * * * * * * * Low phase noise XO output for the 48MHz to 96MHz range (-137 dBc at 10kHz offset). CMOS output. 12 to 24MHz crystal input. Integrated crystal load capacitor: no external load capacitor required. Low jitter (RMS): 3-6ps period, 7-10ps accum. 3.3V operation. Available in 8-Pin TSSOP or SOIC. PIN CONFIGURATION CLK VDD OE XIN 1 2 3 4 8 7 6 5 GND GND N/C XOUT OUTPUT RANGE DESCRIPTIONS The PLL602-41 is a low cost, high performance and low phase noise XO, providing less than -137dBc at 10kHz offset in the 48MHz to 96MHz operating range. The very low jitter (3 to 6 ps RMS period jitter and 7 to 10 ps RMS accumulated jitter) makes this chip ideal for applications requiring reference frequency sources. Input crystal can range from 12 to 24MHz (fundamental resonant mode). MULTIPLIER FREQUENCY RANGE OUTPUT BUFFER X4 48 - 96MHz PLL602-41 CMOS BLOCK DIAGRAM VCO Divider Reference Divider Phase Comparator Charge Pump Loop Filter VCO CLK XIN XOUT OE XTAL OSC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 1 Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) PIN DESCRIPTIONS Name CLK VDD OE XIN XOUT N/C GND Number 1 2 3 4 5 6 7, 8 Type O P I I I P Output clock pin. +3.3V VDD power supply pin. Description Output enable input pin. Disables (tri-state) output when low. Internal pullup enables output by default if pin is not connected to low. Crystal input pin. Crystal output pin. Not connected. Ground pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature Storage Temperature Ambient Operating Temperature TS -65 0 SYMBOL V CC VI VO MIN. MAX. 7 V CC +0.5 V CC +0.5 260 150 70 UNITS V V V C C C -0.5 -0.5 -0.5 Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC Specification PARAMETERS Input Frequency Output Frequency Output Rise Time Output Fall Time Duty Cycle 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 45 50 CONDITIONS MIN. 12 48 TYP. MAX. 24 96 1.5 1.5 55 UNITS MHz MHz ns ns % 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 2 Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) 3. Jitter and Phase Noise specification PARAMETERS Period jitter RMS CONDITIONS With capacitive decoupling between VDD and GND. VIN = 3.3V With capacitive decoupling between VDD and GND. Over 10,000 cycles. VIN = 3.3V 100Hz offset, VIN = 3.3V 1kHz offset, VIN = 3.3V 10kHz offset, VIN = 3.3V 100kHz offset, VIN = 3.3V MIN. TYP. TBM MAX. UNITS ps Accumulated jitter RMS Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier TBM -101 -127 -137 -137 ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz 4. DC Specification PARAMETERS Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Operating Supply Current Short-circuit Current Input Capacitance SYMBOL VDD VIH VIL VIH VIL VOH VOL VOH IDD IS CIN CONDITIONS MIN. 3.135 2 TYP. MAX. 3.465 0.8 UNITS V V V V V V V V For XIN pin For XIN pin IOH = -25mA IOL = 25mA IOH = -8mA No Load OE, Select Pins (VDD/2) + 1 2.4 VDD/2 VDD/2 (VDD/2) - 1 0.4 VDD-0.4 35 120 5 mA mA pF 5. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Capacitance Rating Driving power ESR RS SYMBOL F XIN CL (xtal) MIN. 12 TYP. MAX. 24 UNITS MHz pF mW TBD 1 25 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 3 Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) PACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol A A1 B C D E H L e Min. 1.47 0.10 0.33 0.19 4.80 3.80 5.80 0.38 Max. 1.73 0.25 0.51 0.25 4.95 4.00 6.20 1.27 1.27 BSC Min. 0.05 0.19 0.09 2.90 4.30 6.20 0.45 TSSOP Max. 1.20 0.15 0.30 0.20 3.10 4.50 6.60 0.75 0.65 BSC A1 B e C L A D E H ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PART NUMBER PLL602-41 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP, D=DIE PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 4 |
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